// -----------------------------------------------------------------------------
// -- Copyright (c) 2009 Xilinx, Inc.
// -- This design is confidential and proprietary of Xilinx, All Rights
// Reserved.
// -----------------------------------------------------------------------------
// -   ____  ____
// -  /   /\/   /
// - /___/  \  /   Vendor: Xilinx
// - \   \   \/    Version: 1.0
// -  \   \        Filename: SDR_4TO1_16CHAN_RX.v
// -  /   /        
// - /___/   /\    Date Created: 07/14/2009 
// - \   \  /  \   
// -  \___\/\___\
// - 
// -Revision History:
// -----------------------------------------------------------------------------
/*
--------------------------------------------------------------------------------
Description of module:

The SDR_4TO1_16CHAN_RX module contains all logic in the LVDS Receiver,
including 16 channels of LVDS data, one channel of LVDS clock, a clock/data 
alignment algorithm.
--------------------------------------------------------------------------------
*/
module SDR_4TO1_16CHAN_RX
	(
	DATA_RX_P,
	DATA_RX_N,
	CLOCK_RX_P,
	CLOCK_RX_N,
	INC_PAD,
	DEC_PAD,
	DATA_FROM_ISERDES,
	RESET,
	IDLY_RESET,
	IDELAYCTRL_RESET,
	CLK200,
	TAP_00,
	TAP_01,
	TAP_02,
	TAP_03,
	TAP_04,
	TAP_05,
	TAP_06,
	TAP_07,
	TAP_08,
	TAP_09,
	TAP_10,
	TAP_11,
	TAP_12,
	TAP_13,
	TAP_14,
	TAP_15,
	TAP_CLK,
	TRAINING_DONE,
	RXCLK,
	RXCLKDIV,
	IDELAY_READY
	);

input	[15:0]	DATA_RX_P;		//SERIAL SIDE RX DATA (P)
input	[15:0]	DATA_RX_N;              //SERIAL SIDE RX DATA (N)
input		CLOCK_RX_P;		//FORWARDED CLOCK FROM TX (P)
input		CLOCK_RX_N;             //FORWARDED CLOCK FROM TX (N)
input		INC_PAD;		//MANUAL INCREMENT TO DATA DELAY
input		DEC_PAD;		//MANUAL DECREMENT TO DATA DELAY
input		RESET;			//RX DOMAIN RESET
input		IDLY_RESET;		//IDELAY TAP RESET
input		IDELAYCTRL_RESET;	//IDELAYCTRL CIRCUIT RESET
input		CLK200;			//200 MHZ REFERENCE CLOCK TO IDELAYCTRL

output	[63:0]	DATA_FROM_ISERDES;	//PARALLEL SIDE RX DATA
output	[4:0]	TAP_00;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_01;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_02;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_03;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_04;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_05;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_06;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_07;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_08;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_09;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_10;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_11;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_12;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_13;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_14;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_15;			//IDELAY TAP COUNT (0-32)
output	[4:0]	TAP_CLK;		//IDELAY TAP COUNT ON CLK CHANNEL (0-32)
output		TRAINING_DONE;		//ALIGNMENT OF ALL CHANNELS COMPLETE
output		RXCLK;			//FORWARDED CLOCK FROM TX (BUFIO OUTPUT)
output		RXCLKDIV;               //PARALLEL SIDE RX CLOCK (DIVIDED FROM RXCLK)
output		IDELAY_READY;		//FLAG INDICATING THAT IDELAYCTRL IS LOCKED
wire		CLOCK_RX_BUF;
wire	[15:0]	DATA_RX_BUF;
(*KEEP = "TRUE"*)
wire		CLOCK_RX_IODELAY_OUT;
wire	[3:0]	CLOCK_RX_ISERDES_OUT;

reg	[3:0]	INC_CAPTURE = 0;
reg	[3:0]	DEC_CAPTURE = 0;
reg		INC_PULSE = 0;
reg		DEC_PULSE = 0;
reg	[15:0]	RESET_SM = 0;

integer		I;

assign 		INC_DELAY =	INC_PULSE;
assign 		ICE_DELAY = 	INC_PULSE || DEC_PULSE;
assign		TAP_00 =	5'h00;
assign		TAP_01 =	5'h00;
assign		TAP_02 =	5'h00;
assign		TAP_03 =	5'h00;
assign		TAP_04 =	5'h00;
assign		TAP_05 =	5'h00;
assign		TAP_06 =	5'h00;
assign		TAP_07 =	5'h00;
assign		TAP_08 =	5'h00;
assign		TAP_09 =	5'h00;
assign		TAP_10 =	5'h00;
assign		TAP_11 =	5'h00;
assign		TAP_12 =	5'h00;
assign		TAP_13 =	5'h00;
assign		TAP_14 =	5'h00;
assign		TAP_15 =	5'h00;


//IDELAYCTRL MODULE
//IDELAYCTRL RX_IDELAYCTRL(.RDY(IDELAY_READY), .REFCLK(CLK200), .RST(IDELAYCTRL_RESET));


//SOURCE SYNCHRONOUS CLOCK INPUT
IBUFDS #(
	.DIFF_TERM("TRUE"),
	.IOSTANDARD("LVDS_25")
) SOURCE_SYNC_CLOCK_IN
	(
	.O(CLOCK_RX_BUF), 
	.I(CLOCK_RX_P), 
	.IB(CLOCK_RX_N)
	);


///CLOCK BUFFER FOR SERIAL SIDE CLOCK
BUFIO RX_CLK_BUFIO
	(
	.O(RXCLK), 
	.I(CLOCK_RX_IODELAY_OUT)
	);
///assign RXCLK = CLOCK_RX_IODELAY_OUT;         // change by DDV for ISE report error


//CLOCK BUFFER/DIVIDER FOR PARALLEL SIDE CLOCK
BUFR #(
	.BUFR_DIVIDE("4")
) RX_CLK_BUFR
	(
	.O(RXCLKDIV), 
	.CE(1'b1), 
	.CLR(1'b0), 
	.I(CLOCK_RX_IODELAY_OUT)
	);

ISERDESE1 #(
      .DATA_RATE("SDR"),               // Specify data rate of "DDR" or "SDR
      .DATA_WIDTH(4),                  // Specify data width - For DDR 4,6,8, or 10
                                       // For SDR 2,3,4,5,6,7, or 8 
      .INIT_Q1(1'b0),                  // INIT for Q1 register - 1'b1 or 1'b0
      .INIT_Q2(1'b0),                  // INIT for Q2 register - 1'b1 or 1'b0
      .INIT_Q3(1'b0),                  // INIT for Q3 register - 1'b1 or 1'b0
      .INIT_Q4(1'b0),                  // INIT for Q4 register - 1'b1 or 1'b0
      .INTERFACE_TYPE("NETWORKING"),   // Use model - "MEMORY" or "NETWORKING
      .IOBDELAY("IBUF"),               // Specify outputs where delay chain will be applied
                                       // "NONE", "IBUF", "IFD", or "BOTH
      .OFB_USED("FALSE"),              // Enables the use of D input
      .NUM_CE(1),                      // Define number or clock enables to an integer of 1 or 2
      .SERDES_MODE("MASTER")           // Set SERDES mode to "MASTER" or "SLAVE
   ) ISERDES_inst (
      .O(CLOCK_RX_IODELAY_OUT),        // 1-bit combinatorial output
      .Q1(CLOCK_RX_ISERDES_OUT[003]),  // 1-bit registered output
      .Q2(CLOCK_RX_ISERDES_OUT[002]),  // 1-bit registered output
      .Q3(CLOCK_RX_ISERDES_OUT[001]),  // 1-bit registered output
      .Q4(CLOCK_RX_ISERDES_OUT[000]),  // 1-bit registered output
      .Q5(),                           // 1-bit registered output
      .Q6(),                           // 1-bit registered output
      .SHIFTOUT1(),                    // 1-bit carry output
      .SHIFTOUT2(),                    // 1-bit carry output
      .BITSLIP(1'b0),                  // 1-bit Bitslip input
      .CE1(1'b1),                      // 1-bit clock enable input
      .CE2(1'b0),                      // 1-bit clock enable input
      .CLK(RXCLK),                     // 1-bit clock input
      .CLKB(~RXCLK),                   // 1-bit inverted clock input
      .CLKDIV(RXCLKDIV),               // 1-bit divided clock input
      .D(CLOCK_RX_BUF),                // 1-bit serial data input
      .DDLY(CLOCK_RX_IODELAY_TMP),     // 1-bit clock input from IODELAY
      .OCLK(1'b0),                     // 1-bit high-speed clock input
      .SHIFTIN1(1'b0),                 // 1-bit carry input
      .SHIFTIN2(1'b0),                 // 1-bit carry input
      .RST(RESET)                      // 1-bit set/reset input
   );
      
 
IODELAYE1 # (
      .IDELAY_TYPE ("VARIABLE"),               // Specifies type of tap delay line
      .IDELAY_VALUE (0),                       // Specifies initial starting number of taps (input path)
      .ODELAY_VALUE (0),                       // Specifies initial starting number of taps (output path)
      .REFCLK_FREQUENCY(200.00),               // Sets the tap value
      .DELAY_SRC ("I"),                        // Specifies the input type 
      .HIGH_PERFORMANCE_MODE ("TRUE"),         // Set performance mode to "TRUE" or "FLASE"
      .SIGNAL_PATTERN ("CLOCK"))               // set signal pattern to "CLOCK" or "DATA"
IDELAY_inst (
	.C (RXCLKDIV),                         // 1-bit clock input
	.T (1'b0),                             // 1-bit 3-state control input
	.RST (IDLY_RESET | RESET),             // 1-bit reset input
	.CE (ICE_DELAY | ICE_TO_IODELAY_CLK),  // 1-bit increment/decrement enable input
	.INC (INC_DELAY | INC_TO_IODELAY_CLK), // 1-bit increment/decrement input
	.IDATAIN (CLOCK_RX_BUF),               // 1-bit data input from IOB
	.ODATAIN (1'b0),                       // 1-bit data input from OSERDES/OLOGIC
	.DATAIN (1'b0),                        // 1-bit data input from FPGA
	.CNTVALUEOUT(TAP_CLK),                 // 5-bit tap count value output
	.DATAOUT (CLOCK_RX_IODELAY_TMP)        // 1-bit delayed data output
	);



//MACHINE THAT ADJUSTS DELAY OF CLOCK CHANNEL TO OPTIMIZE SAMPLING POINT 
BUS_ALIGN_MACHINE BUS_ALIGN_MACHINE_0
	(
	.RXCLKDIV(RXCLKDIV),
	.RST(RESET||RESET_SM[15]),
	.SAMPLED_CLOCK(CLOCK_RX_ISERDES_OUT),
	.INC(INC_TO_IODELAY_CLK),
	.ICE(ICE_TO_IODELAY_CLK),
	.DATA_ALIGNED(TRAINING_DONE)
	);


//SHORTEN EACH EXTERNAL INC AND DEC PULSE TO ONE RXCLKDIV CYCLE
always @(posedge RXCLKDIV)
   begin						
      INC_CAPTURE[0] <= INC_PAD;			//ASYNCHRONOUS ENTRY POINT
      DEC_CAPTURE[0] <= DEC_PAD;
      begin
         for(I = 0; I <= 3 - 1; I = I + 1)
         begin
            INC_CAPTURE[I + 1] <= INC_CAPTURE[I];	//METASTABLE FLIP-FLOPS
            DEC_CAPTURE[I + 1] <= DEC_CAPTURE[I];	
         end
      end
      INC_PULSE <= INC_CAPTURE[2] & ~INC_CAPTURE[3];	//STABLE, SINGLE PULSE
      DEC_PULSE <= DEC_CAPTURE[2] & ~DEC_CAPTURE[3];	
   end

//CIRCUIT TO PRODUCE RESET DELAYED BY 20 CYCLES FOR BUS_ALIGN_MACHINE
integer		K;
always @(posedge RXCLKDIV)
	begin
	RESET_SM[0] <= RESET;
        for(K = 0; K <= 15 - 1; K = K + 1)
         begin
            RESET_SM[K+1] <= RESET_SM[K];
         end
	end

//DATA INPUT BUFFERS
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_00(.O(DATA_RX_BUF[00]), .I(DATA_RX_P[00]), .IB(DATA_RX_N[00]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_01(.O(DATA_RX_BUF[01]), .I(DATA_RX_P[01]), .IB(DATA_RX_N[01]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_02(.O(DATA_RX_BUF[02]), .I(DATA_RX_P[02]), .IB(DATA_RX_N[02]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_03(.O(DATA_RX_BUF[03]), .I(DATA_RX_P[03]), .IB(DATA_RX_N[03]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_04(.O(DATA_RX_BUF[04]), .I(DATA_RX_P[04]), .IB(DATA_RX_N[04]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_05(.O(DATA_RX_BUF[05]), .I(DATA_RX_P[05]), .IB(DATA_RX_N[05]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_06(.O(DATA_RX_BUF[06]), .I(DATA_RX_P[06]), .IB(DATA_RX_N[06]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_07(.O(DATA_RX_BUF[07]), .I(DATA_RX_P[07]), .IB(DATA_RX_N[07]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_08(.O(DATA_RX_BUF[08]), .I(DATA_RX_P[08]), .IB(DATA_RX_N[08]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_09(.O(DATA_RX_BUF[09]), .I(DATA_RX_P[09]), .IB(DATA_RX_N[09]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_10(.O(DATA_RX_BUF[10]), .I(DATA_RX_P[10]), .IB(DATA_RX_N[10]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_11(.O(DATA_RX_BUF[11]), .I(DATA_RX_P[11]), .IB(DATA_RX_N[11]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_12(.O(DATA_RX_BUF[12]), .I(DATA_RX_P[12]), .IB(DATA_RX_N[12]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_13(.O(DATA_RX_BUF[13]), .I(DATA_RX_P[13]), .IB(DATA_RX_N[13]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_14(.O(DATA_RX_BUF[14]), .I(DATA_RX_P[14]), .IB(DATA_RX_N[14]));
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_15(.O(DATA_RX_BUF[15]), .I(DATA_RX_P[15]), .IB(DATA_RX_N[15]));
                                                                                                   

//ISERDES IN DATA PATH                                                                                                    
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_00(.Q1(DATA_FROM_ISERDES[048]), .Q2(DATA_FROM_ISERDES[032]), .Q3(DATA_FROM_ISERDES[016]), .Q4(DATA_FROM_ISERDES[000]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[00]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_01(.Q1(DATA_FROM_ISERDES[049]), .Q2(DATA_FROM_ISERDES[033]), .Q3(DATA_FROM_ISERDES[017]), .Q4(DATA_FROM_ISERDES[001]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[01]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_02(.Q1(DATA_FROM_ISERDES[050]), .Q2(DATA_FROM_ISERDES[034]), .Q3(DATA_FROM_ISERDES[018]), .Q4(DATA_FROM_ISERDES[002]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[02]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_03(.Q1(DATA_FROM_ISERDES[051]), .Q2(DATA_FROM_ISERDES[035]), .Q3(DATA_FROM_ISERDES[019]), .Q4(DATA_FROM_ISERDES[003]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[03]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_04(.Q1(DATA_FROM_ISERDES[052]), .Q2(DATA_FROM_ISERDES[036]), .Q3(DATA_FROM_ISERDES[020]), .Q4(DATA_FROM_ISERDES[004]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[04]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_05(.Q1(DATA_FROM_ISERDES[053]), .Q2(DATA_FROM_ISERDES[037]), .Q3(DATA_FROM_ISERDES[021]), .Q4(DATA_FROM_ISERDES[005]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[05]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_06(.Q1(DATA_FROM_ISERDES[054]), .Q2(DATA_FROM_ISERDES[038]), .Q3(DATA_FROM_ISERDES[022]), .Q4(DATA_FROM_ISERDES[006]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[06]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_07(.Q1(DATA_FROM_ISERDES[055]), .Q2(DATA_FROM_ISERDES[039]), .Q3(DATA_FROM_ISERDES[023]), .Q4(DATA_FROM_ISERDES[007]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[07]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_08(.Q1(DATA_FROM_ISERDES[056]), .Q2(DATA_FROM_ISERDES[040]), .Q3(DATA_FROM_ISERDES[024]), .Q4(DATA_FROM_ISERDES[008]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[08]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_09(.Q1(DATA_FROM_ISERDES[057]), .Q2(DATA_FROM_ISERDES[041]), .Q3(DATA_FROM_ISERDES[025]), .Q4(DATA_FROM_ISERDES[009]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[09]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_10(.Q1(DATA_FROM_ISERDES[058]), .Q2(DATA_FROM_ISERDES[042]), .Q3(DATA_FROM_ISERDES[026]), .Q4(DATA_FROM_ISERDES[010]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[10]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_11(.Q1(DATA_FROM_ISERDES[059]), .Q2(DATA_FROM_ISERDES[043]), .Q3(DATA_FROM_ISERDES[027]), .Q4(DATA_FROM_ISERDES[011]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[11]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_12(.Q1(DATA_FROM_ISERDES[060]), .Q2(DATA_FROM_ISERDES[044]), .Q3(DATA_FROM_ISERDES[028]), .Q4(DATA_FROM_ISERDES[012]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[12]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_13(.Q1(DATA_FROM_ISERDES[061]), .Q2(DATA_FROM_ISERDES[045]), .Q3(DATA_FROM_ISERDES[029]), .Q4(DATA_FROM_ISERDES[013]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[13]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_14(.Q1(DATA_FROM_ISERDES[062]), .Q2(DATA_FROM_ISERDES[046]), .Q3(DATA_FROM_ISERDES[030]), .Q4(DATA_FROM_ISERDES[014]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[14]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
//ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_15(.Q1(DATA_FROM_ISERDES[063]), .Q2(DATA_FROM_ISERDES[047]), .Q3(DATA_FROM_ISERDES[031]), .Q4(DATA_FROM_ISERDES[015]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[15]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));

///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_00(.Q1(DATA_FROM_ISERDES[063]), .Q2(DATA_FROM_ISERDES[047]), .Q3(DATA_FROM_ISERDES[031]), .Q4(DATA_FROM_ISERDES[015]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[00]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_01(.Q1(DATA_FROM_ISERDES[062]), .Q2(DATA_FROM_ISERDES[046]), .Q3(DATA_FROM_ISERDES[030]), .Q4(DATA_FROM_ISERDES[014]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[01]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_02(.Q1(DATA_FROM_ISERDES[061]), .Q2(DATA_FROM_ISERDES[045]), .Q3(DATA_FROM_ISERDES[029]), .Q4(DATA_FROM_ISERDES[013]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[02]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_03(.Q1(DATA_FROM_ISERDES[060]), .Q2(DATA_FROM_ISERDES[044]), .Q3(DATA_FROM_ISERDES[028]), .Q4(DATA_FROM_ISERDES[012]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[03]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_04(.Q1(DATA_FROM_ISERDES[059]), .Q2(DATA_FROM_ISERDES[043]), .Q3(DATA_FROM_ISERDES[027]), .Q4(DATA_FROM_ISERDES[011]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[04]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_05(.Q1(DATA_FROM_ISERDES[058]), .Q2(DATA_FROM_ISERDES[042]), .Q3(DATA_FROM_ISERDES[026]), .Q4(DATA_FROM_ISERDES[010]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[05]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_06(.Q1(DATA_FROM_ISERDES[057]), .Q2(DATA_FROM_ISERDES[041]), .Q3(DATA_FROM_ISERDES[025]), .Q4(DATA_FROM_ISERDES[009]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[06]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_07(.Q1(DATA_FROM_ISERDES[056]), .Q2(DATA_FROM_ISERDES[040]), .Q3(DATA_FROM_ISERDES[024]), .Q4(DATA_FROM_ISERDES[008]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[07]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_08(.Q1(DATA_FROM_ISERDES[055]), .Q2(DATA_FROM_ISERDES[039]), .Q3(DATA_FROM_ISERDES[023]), .Q4(DATA_FROM_ISERDES[007]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[08]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_09(.Q1(DATA_FROM_ISERDES[054]), .Q2(DATA_FROM_ISERDES[038]), .Q3(DATA_FROM_ISERDES[022]), .Q4(DATA_FROM_ISERDES[006]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[09]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_10(.Q1(DATA_FROM_ISERDES[053]), .Q2(DATA_FROM_ISERDES[037]), .Q3(DATA_FROM_ISERDES[021]), .Q4(DATA_FROM_ISERDES[005]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[10]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_11(.Q1(DATA_FROM_ISERDES[052]), .Q2(DATA_FROM_ISERDES[036]), .Q3(DATA_FROM_ISERDES[020]), .Q4(DATA_FROM_ISERDES[004]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[11]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_12(.Q1(DATA_FROM_ISERDES[051]), .Q2(DATA_FROM_ISERDES[035]), .Q3(DATA_FROM_ISERDES[019]), .Q4(DATA_FROM_ISERDES[003]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[12]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_13(.Q1(DATA_FROM_ISERDES[050]), .Q2(DATA_FROM_ISERDES[034]), .Q3(DATA_FROM_ISERDES[018]), .Q4(DATA_FROM_ISERDES[002]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[13]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_14(.Q1(DATA_FROM_ISERDES[049]), .Q2(DATA_FROM_ISERDES[033]), .Q3(DATA_FROM_ISERDES[017]), .Q4(DATA_FROM_ISERDES[001]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[14]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
///ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_15(.Q1(DATA_FROM_ISERDES[048]), .Q2(DATA_FROM_ISERDES[032]), .Q3(DATA_FROM_ISERDES[016]), .Q4(DATA_FROM_ISERDES[000]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(!DATA_RX_BUF[15]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));

ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_00(.Q1(DATA_FROM_ISERDES[048]), .Q2(DATA_FROM_ISERDES[032]), .Q3(DATA_FROM_ISERDES[016]), .Q4(DATA_FROM_ISERDES[000]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[00]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_01(.Q1(DATA_FROM_ISERDES[049]), .Q2(DATA_FROM_ISERDES[033]), .Q3(DATA_FROM_ISERDES[017]), .Q4(DATA_FROM_ISERDES[001]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[01]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_02(.Q1(DATA_FROM_ISERDES[050]), .Q2(DATA_FROM_ISERDES[034]), .Q3(DATA_FROM_ISERDES[018]), .Q4(DATA_FROM_ISERDES[002]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[02]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_03(.Q1(DATA_FROM_ISERDES[051]), .Q2(DATA_FROM_ISERDES[035]), .Q3(DATA_FROM_ISERDES[019]), .Q4(DATA_FROM_ISERDES[003]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[03]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_04(.Q1(DATA_FROM_ISERDES[052]), .Q2(DATA_FROM_ISERDES[036]), .Q3(DATA_FROM_ISERDES[020]), .Q4(DATA_FROM_ISERDES[004]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[04]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_05(.Q1(DATA_FROM_ISERDES[053]), .Q2(DATA_FROM_ISERDES[037]), .Q3(DATA_FROM_ISERDES[021]), .Q4(DATA_FROM_ISERDES[005]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[05]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_06(.Q1(DATA_FROM_ISERDES[054]), .Q2(DATA_FROM_ISERDES[038]), .Q3(DATA_FROM_ISERDES[022]), .Q4(DATA_FROM_ISERDES[006]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[06]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_07(.Q1(DATA_FROM_ISERDES[055]), .Q2(DATA_FROM_ISERDES[039]), .Q3(DATA_FROM_ISERDES[023]), .Q4(DATA_FROM_ISERDES[007]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[07]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_08(.Q1(DATA_FROM_ISERDES[056]), .Q2(DATA_FROM_ISERDES[040]), .Q3(DATA_FROM_ISERDES[024]), .Q4(DATA_FROM_ISERDES[008]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[08]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_09(.Q1(DATA_FROM_ISERDES[057]), .Q2(DATA_FROM_ISERDES[041]), .Q3(DATA_FROM_ISERDES[025]), .Q4(DATA_FROM_ISERDES[009]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[09]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_10(.Q1(DATA_FROM_ISERDES[058]), .Q2(DATA_FROM_ISERDES[042]), .Q3(DATA_FROM_ISERDES[026]), .Q4(DATA_FROM_ISERDES[010]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[10]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_11(.Q1(DATA_FROM_ISERDES[059]), .Q2(DATA_FROM_ISERDES[043]), .Q3(DATA_FROM_ISERDES[027]), .Q4(DATA_FROM_ISERDES[011]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[11]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_12(.Q1(DATA_FROM_ISERDES[060]), .Q2(DATA_FROM_ISERDES[044]), .Q3(DATA_FROM_ISERDES[028]), .Q4(DATA_FROM_ISERDES[012]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[12]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_13(.Q1(DATA_FROM_ISERDES[061]), .Q2(DATA_FROM_ISERDES[045]), .Q3(DATA_FROM_ISERDES[029]), .Q4(DATA_FROM_ISERDES[013]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[13]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_14(.Q1(DATA_FROM_ISERDES[062]), .Q2(DATA_FROM_ISERDES[046]), .Q3(DATA_FROM_ISERDES[030]), .Q4(DATA_FROM_ISERDES[014]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[14]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
ISERDESE1 #(.DATA_RATE("SDR"), .DATA_WIDTH(4), .INTERFACE_TYPE("NETWORKING"), .NUM_CE(1), .SERDES_MODE("MASTER")) ISERDES_RX_DATA_15(.Q1(DATA_FROM_ISERDES[063]), .Q2(DATA_FROM_ISERDES[047]), .Q3(DATA_FROM_ISERDES[031]), .Q4(DATA_FROM_ISERDES[015]), .Q5(), .Q6(), .O(), .SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b0), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_BUF[15]), .OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET));
         
         
endmodule 


